2011/10/17 Test 印出

依上星期範例
修改測試

程式碼

module top;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);
mux Ml(OUT,A,B,SEL);
endmodule
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

時邁圖

 ------------------------------------------------------------

"hello verilog"

原版

module hello1;
initial $display("Hello Verilog");
endmodule

 印出

如果改成這樣

module hello2; initial $display("Hello Verilog");endmodule

或是這樣

module
hello3;
initial
$display(
"Hello Verilog"
                           )
                          ;
endmodule

結果依然相同
但是 "Hello Verilog" 的 "" 不可和 Hello Verilog 分離
否則會出錯    ↓